The present invention relates to DRAM circuits and, more specifically to a circuit and method for ensuring that correct data is output from a high speed DRAM with a correct read latency.
A typical DRAM memory system has an external DRAM controller which makes read and write requests of a DRAM memory device. When making a read request the controller expects data within the memory device to be available on a data bus with a predetermined read latency which is usually a predetermined number of external system clock cycles after a read request is made by the controller e.g., eight external clock cycles. Internally, the DRAM memory device has its own clock system which receives the external clock signal and develops from the external clock several different internal clock signals for internal operation of the memory device.
The internal clock system of a known high speed memory device produces at least two clock domains. The first clock domain represents tie timing used in the bulk of the logic circuits and to drive the memory array core. The timing for the first domain is produced from a buffered external free running system clock. The phase of the clock signal in the first domain relative to the external clock is dependent upon a clock receiver and clock tree delays. The second domain, also derived from the external system clock, represents the timing of a back-timed read clock. This clock domain is produced by a delay lock loop (DLL). This second clock domain produces a read clock, for operating data read latches. The read clock is provided to the read latch with a desired phase relationship to the external system clock. The second clock domain compensates for delays in the data output (Do) path in order to produce a read clock signal which operates the output data latches to achieve a specified phase alignment with the external system clock. Neither of these two clock domains truly accurately reflects the timing of the external system clock, particularly at high frequencies of operation and the timing of the clock signals in the two domains may criss-cross one another during memory device operation due to process, voltage and temperature (PVT) variations. This may cause a problem in that one clock domain responsible for delivery of read data to an output latch may cause this data to be delivered at a different time from when the back-timed read clock for latching that data is present at the latch.
In order to meet a specified read latency the memory device must be able to count clock signals following receipt of a READ command and activate the output latch to latch output data with the back-timed read clock at the precise time necessary to produce the specified read latency. This is difficult when the first and second clock domains keep criss-crossing each other.
Since the amount of read clock back-timing becomes indeterminate relative to the data availability, it is very difficult to control the read clock and guarantee a correct data output and a specific read latency as measured in external clock cycles.
The present invention provides a method and apparatus for compensating for uncertainty and variations in the amount of read clock back timing relative to data flow in order to obtain a correct data output at a specified read latency as measured in external clock cycles.
In the invention a start signal is transferred from the external system clock domain to the internal read clock domain so that the start signal has a fixed timing relationship to the read clock. The start signal tracks any changes in the read clock timing and is used to guarantee that read data from a memory array and a read clock are properly synchronized at the output of a memory device.
The start signal is generated by a command decoder upon receipt of a READ command and is passed through a delay line which is slaved to the delay locked loop (DLL) delay line which is used to back-time the read clock. After passing through the slaved delay line the start signal will have the same phase and back-timing relative to the external clock as the read clock.
A counter is pre-loaded with a value provided by a mode register and an offset register. This value represents a desired read latency minus a measured delay in providing a read clock signal through the DLL, clock tree, output latch, and output driver. The counter will count to a specified value using the read clock following receipt of the start signal. The actual count value pre-loaded into the counter may be further offset by one or more counts to allow for decoding or other miscellaneous delays within the memory device. When the counter reaches the specified value it courses the output circuit which receives the read data and read clock to synchronically latch the read data and output the read data with a specified read latency.
Thus, even if the back-timing of the read clock output varies and criss-crosses a clock cycle boundary, the start signal will move with it, keeping the operation of the data and read clock synchronized.